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EDI2DL32256V
256Kx32 Synchronous Pipline Burst SRAM 3.3V
FEATURES
s tKHQV times of 3.5, 3.8 and 4.0ns s 166, 150 and 133 MHz clock speed s DSP Memory Solution * Texas Instruments' TMS320C6201 * Texas Instruments' TMS320C67x s Package: * 119 pin BGA, JEDEC MO-163 s 3.3V Operating Supply Voltage s 3.5ns Output Enable access time s Single Write Control and Output Enable Lines s Single Chip Enable Line s 56% space savings vs. monolithic TQFPs s Multiple VCC and VSS pins s Reduced inductance and capacitance
DESCRIPTION
The EDI2DL32256VxxBC is a 3.3V, 256Kx32 Synchronous Pipeline Burst SRAM constructed with two 256Kx16 die mounted on a multi-layer laminate substrate. The device is packaged in a 119 lead, 14mm by 22mm, BGA. It is available with clock speeds of166, 150 and 133 MHz. The device is a Pipeline Burst SRAM, allowing the user to develop a fast external memory for Texas Instruments' "C6x". In Burst Mode data from the first memory location is available in three clock cycles, while the subsequent data is available in one clock cycle (3/1/1/1). Subsequent burst addresses are generated by the TMS320C6x DSP. Individual address locations can also be read, allowing one memory access in 3 clock cycles. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, chip enable (CE\), burst control input (ADSC\), byte write enables (BW0\ to BW3\) and Write Enable (BWE\). Asynchronous inputs include the output enable (OE\), burst mode control (MODE), and sleep mode control (ZZ). The data outputs (DQ), enabled by OE\, are also asynchronous. Address lines and the chip enable are registered with the address status controller (ADSC\) input pin.
FIG. 1
PIN CONFIGURATION
1 A B C D E F G H J K L M N P R T U VDD NC NC DQ16 DQ18 VDD DQ21 DQ23 VDD DQ31 DQ29 VDD DQ26 DQ24 NC NC VDD 1 2 A NC A NC DQ17 DQ19 DQ20 DQ22 VDD DQ30 DQ28 DQ27 DQ25 NC A NC NC 2 3 A A A VSS VSS VSS BE2\ VSS NC VSS BE3\ VSS VSS VSS MODE A NC 3 4 NC ADSC\ VDD NC CE\ OE\ NC NC VDD CLK NC BWE\ A1 A0 VDD A NC 4 5 A A A VSS VSS VSS BE1\ VSS NC VSS BE0\ VSS VSS VSS NC A NC 5 6 A A A NC DQ9 DQ11 DQ12 DQ14 VDD DQ6 DQ4 DQ3 DQ1 NC A NC NC 6 7 VDD NC NC DQ8 DQ10 VDD DQ13 DQ15 VDD DQ7 DQ5 VDD DQ2 DQ0 NC ZZ VDD 7 A B C D E F G H J K L M N P R T U
256K X 16 SSRAM
BLOCK DIAGRAM
A0-17 CLK ADSC\ OE\ BWE\ CE\ MODE ZZ BE0\ BE1\ BE2\ BE3\ DQ0-7 DQ8-15 DQ16-23 DQ24-31
256K X 16 SSRAM
November 2000, Rev. 1 ECO #13417
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White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com
EDI2DL32256V
PIN DESCRIPTIONS
Pin Various L5,G5 G3,L3 M4 K4 E4 F4 B4 R3 T7 Various Various Various Symbol A0-17 BE0\,BE1\, BE2\,BE3\ BWE\ CLK CE\ OE\ ADSC\ MODE ZZ DQ0-31 Vcc Vss Type Input Synchronous Input Synchronous Input Synchronous Input Synchronous Input Synchronous Input Input Synchronous Input Input Synchronous Input/Output Supply Ground Description Addresses: These inputs are registered and must meet setup and hold times around the rising edge of CLK. Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ BE2\, BE3\ cycle. BE0\ controls DQ0-7. BE1\ controls DQ8-15. BE2\ controls DQ16-23. BE3\ controls DQ24-31 Byte Write Enable: This active LOW input gates byte write operations and must meet the setup and hold times around the rising edge of CLK. Clock:This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clockis rising edge. Chip Enable: This active LOW inputs is used to enable the device. Output Enable: This active LOW asynchronous input enables the data output drivers Address Status Controller: This active LOW input causes device to be deselected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. Static Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED BURST. Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal operation, this input has to be either LOW or NC (no connect) Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31 Core power supply: +3.3V -5%/+5% Ground
TRUTH TABLE
Operation Deselected Cycle, Power Down WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Address Used None External External External Current Current Current Current Current Current CE\ H L L L X X H H X H ADSC\ L L L L H H H H H H WRITE\ X L H H H H H H L L OE\ X X L H L H L H X X DQ High-Z D Q High-Z Q High-Z Q High-Z D D
NOTE: 1. X means idonit carei, H means logic HIGH. L means logic LOW. 2a.WRITE\ = L, means [BE0\*BE1\*BE2\*BE3\]*BWE\ equals LOW 2b.WRITE\ = H, means [BE0\*BE1\*BE2\*BE3\]*BWE\ equals HIGH 3. All inputs except OE\ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 4. Suspending burst generates wait cycle 5. For a write operation following a read operation, OE\ must be HIGH before the input data required setup time plus High-Z time for OE\ and staying HIGH though out the input data hold time. 6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
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November 2000, Rev. 1 ECO #13417
EDI2DL32256V
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss VIN Storage Temperature Junction Temperature Power Dissipation Short Circuit Output Current (per I/O) -0.5V to 4.6V -0.5V to Vcc+0.5V -55C to +110C +110C 3 Watts 20 mA
RECOMMENDED OPERATING CONDITIONS
Description Input High Voltage Input Low Voltage Supply Voltage Symbol VIH VIL Vcc Min 2 -0.3 3.135 Max Vcc+0.3 0.7 3.465 Unit V V V
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (f = 1MHz, VIN = VCC or VSS)
Parameter Address Lines Data Lines Control Lines Symbol CA CD/Q CC Max TBD TBD TBD Unit pF pF pF
PARTIAL TRUTH TABLE
Function READ WRITE one Byte (DQ0-7) WRITE all Bytes BWE\ H L L BE0\ X L L BE1\ X H L BE2\ X H L BE\3 X H L
DC ELECTRICAL CHARACTERISTICS (f = 1MHz, VIN = VCC or Vss)
Parameter Power Supply Current: Operating CMOS Standby TTL Standby TTL Standby Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Symbol ICC1 ISB2 ISB3 ISB4 ILI ILO VOH VOL Conditions Device Selected; all inputs VIL or VIH; cycle time tKC MIN; VCC = MAX; outputs open Device deselected; VCC = MAX; all inputs VSS +0.2 or VCC -0.2; all inputs static; CLK frequency = 0 Device deselected; all inputs VIL or VIH; all inputs static; VCC = MAX; CLK frequency = 0 Device deselected; all inputs VIL or VIH; VCC = MAX; CLK cycle time tCK MIN 0V < VIN < VCC Output(s) disabled, 0V VOUT VCC IOH = -2.0mA IOL = 2.0mA Min Max 850 20 40 40 -2 -2 2.4 2 2 0.7 Units mA mA mA mA A A V V
AC TEST CIRCUIT
Parameter
AC TEST CONDITIONS
I/O VSS to 2.5 1.8 1.25 See figure, at left Unit V ns V
Output
Z0 == 50 Z0 50
Input Pulse Levels Input Rise and Fall Times (max) Input and Output Timing Levels Output Load
50
Vt = 1.5V 1.25V
AC Output Load Equivalent
November 2000, Rev. 1 ECO #13417
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EDI2DL32256V
AC ELECTRICAL CHARACTERISTICS
Description Clock Clock cycle time Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output in Low-Z Clock to output in High-Z OE to output valid OE to output in Low-Z OE to output in High-Z Setup Times Address Status Controller valid to Clock Address valid to Clock Chip Enable valid to Clock Write Enable (BWE\) valid to Clock Data Valid to Clock Hold Times Address Status Controller Hold time Address Hold time Chip Enable Hold time Write Enable (BWE\) Hold time Data Hold time tKHSCX tKHAX tKHEX tKHWX tKHDX 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 tSCVKH tAVKH tEVKH tWLKH tDVKH 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 tKHQV tKHQX tKHQZ tOELQV tOELQX tOEHQZ 0 3.5 0 1.5 6 3.5 0 3.5 3.5 0 1.5 6.7 3.5 0 3.8 3.8 0 1.5 7.5 3.8 4.0 tKHKH tKHKL tKLKH 6 2.4 2.4 6.7 2.6 2.6 7.5 2.8 2.8 Symbol Min 3.5ns Max Min 3.8ns Max Min 4.0ns Max Units
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November 2000, Rev. 1 ECO #13417
EDI2DL32256V
FIG. 2
READ TIMING
tKHKH tKHKL tKLKH
CLK
tSC VKH tKHSC X
ADSC\
tEVKH
CE\
tKHEX tAVKH
ADDR
A1
tKHAX
A2
A3
A4
A5
OE\
tOELQ X tOELQ V tOEHQZ
WRITE\
tKHQ Z tKHQ X
tKHQ V
DQ
Q(A1)
Q(A2)
Q(A3)
Q(A4)
Q(A5)
November 2000, Rev. 1 ECO #13417
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EDI2DL32256V
FIG. 3
WRITE TIMING
tKHK H tKHKL tKLKH
CLK
t SC VKH t KHSCX
ADSC\
t EVKH
CE\
t KHEX t AVKH
ADDR
A1
t KHAX
A2
A3
A4
A5
OE\
t WVKH
KHG WX
t KHWX
WRITE\
t DVK H
t KHDX
DQ
D(A1)
D(A2)
D(A3)
D (A4)
D(A5)
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November 2000, Rev. 1 ECO #13417
EDI2DL32256V
ORDERING INFORMATION
Commercial Temperature Range (0C to +70C) Part Number tKQ (ns) Clock Frequency (MHz) EDI2DL32256V35BC 3.5 166 EDI2DL32256V38BC EDI2DL32256V40BC 3.8 4.0 150 133 Package No. TBD TBD TBD Industrial Temperature Range (-40C to +85C) Part Number tKQ (ns) Clock Frequency (MHz) EDI2DL32256V40BI 4.0 133 Package No. TBD
PACKAGE DESCRIPTION:
JEDEC MO-163
0.300 BSC
119 LEAD BGA
0.110 MAX R 0.062 MAX (4x)
A B C D E F G
PIN 1 INDEX
0.551 BSC
0.050 TYP 0.866 BSC
0.800 BSC
H J K L M N P R T U
0.050 TYP
0.028 MAX
ALL DIMENSIONS ARE IN INCHES
November 2000, Rev. 1 ECO #13417
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White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com
EDI2DL32256V
FIG. 5
INTERFACING THE TEXAS INSTRUMENTS TMS320C6201 WITH THE EDI2DL32256V (256Kx32 SSRAM)
EA0-22
(NOTE 1)
A0-17
CE2\ CE1\ CE0\ CE\ MODE
(NOTE 4)
NC, Vss, Vcc
BE3\ Texas Instruments BE2\ TMS320C6201 BE1\ BE0\ SSOE\ SSADS\ SSADV\ SSWE\ CLKOUT1 CLKOUT2
ZZ (NOTE 2) BE3\ BE2\ EDI2DL32256V BE1\ BE0\ OE\ ADSC\ ADV\ GW\ (NOTE 3) CLK
ED0-31
DQ0-31
NOTES: 1. Either CE0 or CE2 can be used to enable the device. 2. When the ZZ pin is asserted HIGH, the device will be in CMOS standby mode regardless of the state of any other pins. While in standby mode the device will take one complete Clock cycle to become active again after a LOW is asserted on the ZZ pin. One possible option for the designer concerned about power is to tie the ZZ signal to the chip enable they are using for the device. Any time the chip is disabled (by driving the chip enable pin HIGH) the device will go into standby mode. Standby mode can also be achieved by tying the ZZ pin LOW or allowing it to float and meeting all the signal conditions specified in the data sheet. 3. Use CLKOUT1 for running the memory at the same clock speed as the C6x. Use CLKOUT2 for running the SBSRAM at one half the clock rate of the C6x. 4. The MODE pin can be tied to Vss (Linear Burst), tied to Vcc (Interleaved Burst) or allowed to float (Interleaved Burst).
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November 2000, Rev. 1 ECO #13417

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